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clock generator for intel ? eaglelake chipset sl28506-2 rev 1.3 june 18, 2008 page 1 of 28 2200 laurelwood road, santa clara, ca 95054 tel:(40 8) 855-0555 fax:(408) 855-0550 www.spectralinear.co m features ? compliant to intel ? ck505 ? selectable cpu frequencies ? src clocks compliant to pci-express gen2 (except src0 and src1) ? differential cpu clock pairs ? 100 mhz differential src clocks ? 100 mhz differential lcd clock ? 96 mhz differential dot clock ? 48 mhz usb clocks ? 33 mhz pci clock ? 25 mhz wol or pata clock on se ? 27 mhz non-spread video clock on se ? 1394a and 1394b clocks on se ? buffered reference clock 14.318 mhz ? low-voltage frequency select input ? i 2 c support with readback capabilities ? triangular spread spectrum profile for maximum electromagnetic interference (emi) reduction ? 3.3v power supply/0.7v for diff ios ? 56-pin tssop/ssop table 1. output configuration table cpu src pci ref dot96 usb_48m se lcd x2/x3 x5/9 x6 x 1 x 1 x 1 x0/x2 x0/x1 pin configuration block diagram pci_0 / oe#_0/2_a 1 56 sclk vdd_pci 2 55 sdata pci_1 / oe#_1/4_a 3 54 ref0 / fsc / test_sel pci_2 / tme 4 53 vdd_ref pci_3 / cfg0* 5 52 xtal_in pci_4 / src5_en 6 51 xtal_out pcif_0 / itp_en 7 50 vss_ref vss_pci 8 49 fsb / test_mode vdd_48 9 48 ck_pwrgd / pw rdw n# usb_48 / fsa 10 47 vdd_cpu vss_48 11 46 cpu0 vdd_io 12 45 cpu0# src0 / dot96 13 44 vss_cpu src0# / dot96# 14 43 cpu1 vss_io 15 42 cpu1# vdd_pll3 16 41 vdd_cpu_io src1 / lcd_100/se1 17 40 io_vout src1# / lcd_100#/se2 18 39 src8 / cpu2_itpt vss_pll3 19 38 src8# / cpu2_itpc vdd_pll3_io 20 37 vdd_src_io src2 / sata 21 36 src7 / oe#_8 src2# / sata# 22 35 src7# / oe#_6 vss_src 23 34 vss_src src3/oe#_0/2_b 24 33 src6 src3# / oe#_1/4_b 25 32 src6# vdd_src_io 26 31 vdd_src src4 27 30 src5 / pci_stop# src4# 28 29 src5# / cpu_stop# * internal pull-down sl28506-2
sl28506-2 rev 1.3 june 18, 2008 page 2 of 28 pin definitions pin no. name type description 1 pci_0/oe#_0/2_a i/o, se 33 mhz clock/3.3v oe# input mappable via i2c to control either src 0 or src 2. default pci0 2 vdd_pci pwr 3.3v power supply for pci pll. 3 pci_1/oe#_1/4_a i/o, se 33 mhz clock/3.3v oe# input mappable via i2c to control either src 1 or src 4. default pci1. 4 pci_2/tme i/o, se 3.3v tolerance input for overclock ing enable pin 33 mhz clock. refer to dc electrical specifications table for vil _fs and vih_fs specifica- tions. 5 pci_3/cfg0 i/o, se, pd 3.3v tolerant input for cpu frequency selection/33 mhz clock. refer to dc electrical specifications table for vil _pci3/cfg0 and vih_pci3/cfg0 specifications . 6 pci_4/src5_sel i/o, se 3.3v tolerant input to enable src5/33 mhz clock output. (sampled on the ck_pwrgd assertion) 1 = src5, 0 = cpu_stop# 7 pcif_0/itp_en i/o, se 3.3v lvttl input to enable sr c8 or cpu2_itp/33 mhz clock output. (sampled on the ck_pwrgd assertion) 1 = cpu2_itp, 0 = src8 8 vss_pci gnd ground for outputs. 9 vdd_48 pwr 3.3v power supply for outputs and pll. 10 usb_48/fsa i/o 3.3v tolerant input for cpu freque ncy selection/fixed 48 mhz clock output. refer to dc electrical specifications table for vil _fs and vih_fs specifica- tions. 11 vss_48 gnd ground for outputs. 12 vdd_io pwr 0.7v power supply for outputs. 13 src0/dot96 o, dif 100 mhz differential serial refe rence clocks/fixed 96 mhz clock output. selected via i2c default is src0. 14 src0#/dot96# o, dif 100 mhz differential serial ref erence clocks/fixed 96 mhz clock output. selected via i2c default is src0. 15 vss_io gnd ground for pll2. 16 vdd_pll3 pwr 3.3v power supply for pll3 17 src1/lcd_100/se1 o, dif, se 100 mhz differential serial reference clocks/100 mh z lcd video clock/se1 and se2 clocks. default src1 18 src1#/lcd_100#/se2 o, dif, se 100 mhz differential serial reference clocks/100 mh z lcd video clock/se1 and se2 clocks. default src1 19 vss_pll3 gnd ground for pll3. 20 vdd_pll3_io pwr 0.7v power supply for pll3 outputs . 21 src2/sata o, dif 100 mhz differential serial refere nce clocks / 100mhz sata clock 22 src2#/sata# o, dif 100 mhz differential serial refe rence clocks / 100mhz sata clock 23 vss_src gnd ground for outputs. 24 src3/oe#_0/2_b i/o, dif 100-mhz differential serial reference clocks / 3.3v oe#_0/2_b, input, mappable via i2c to control either src 0 or src 2 25 src3#/oe#_1/4_b i/o, dif 100-mhz differential serial reference clocks / 3.3v oe#_1/4_b input, mappable via i2c to control either src 1 or src 4. default src3 26 vdd_src_io pwr 0.7v power supply for src outputs. 27 src4 o, dif 100 mhz differential serial reference c locks. 28 src4# o, dif 100 mhz differential serial reference clocks. 29 src5#/pci_stop# i/o, dif 3.3v tolerant input for stopping pci and src output s /100 mhz differential serial reference clocks.
sl28506-2 rev 1.3 june 18, 2008 page 3 of 28 30 src5/cpu_stop# i/o, dif 3.3v tolerant input for stopping cpu outputs/100 mh z differential serial reference clocks. 31 vdd_src pwr 3.3v power supply for src pll. 32 src6# o, dif 100 mhz differential serial reference clocks. 33 src6 o, dif 100 mhz differential serial reference c locks. 34 vss_src gnd ground for outputs. 35 src7#/oe#_6 i/o, dif 100 mhz differential serial reference clocks/3.3v o e#6 input controlling src6. default src7. 36 src7/oe#_8 i/o, dif 100 mhz differential serial reference clocks/3.3v o e#8 input controlling src8. default src7. 37 vdd_src_io pwr 0.7v power supply for src outputs. 38 src8#/cput2_itp# o, dif selectable differential cp u or src clock output. itp_en = 0 @ ck_pwrgd assertion = src8 itp_en = 1 @ ck_pwrgd assertion = cpu2 note: cpu2 is an iamt clock in iamt mode depending on the configuration set in byte 11 bit3:2. 39 src8/cpuc2_itp o, dif selectable differential cpu o r src clock output. itp_en = 0 @ ck_pwrgd assertion = src8 itp_en = 1 @ ck_pwrgd assertion = cpu2 note: cpu2 is an iamt clock in iamt mode depending on the configuration set in byte 11 bit3:2. 40 io_vout o integrated linear regulator control. 41 vdd_cpu_io pwr 0.7v power supply for cpu outputs. 42 cpu1# o, dif differential cpu clock outputs. note: cpu1 is an iamt clock in iamt mode depending on the configuration set in byte 11 bit3: 2. 43 cpu1 o, dif differential cpu clock outputs. note: cpu1 is an iamt clock in iamt mode depending on the configuration set in byte 11 bit3: 2. 44 vss_cpu gnd ground for outputs. 45 cpu0# o, dif differential cpu clock outputs. 46 cpu0 o, dif differential cpu clock outputs. 47 vdd_cpu pwr 3.3v power supply for cpu pll. 48 ck_pwrgd/pwrdwn# i 3.3v lvttl input. this pin is a level sensitive strobe used to latch the fs_a, fs_b, fs_c, fs_d, src5_sel, and itp_en. after ck_pwrgd (active high) assertion, this pin be comes a real-time input for asserting power down (active low). 49 fsb/test_mode i 3.3v tolerant input for cpu frequen cy selection. selects ref/n or tri-state when in test mode 0 = tri-state, 1 = ref/n. refer to dc electrical specifications table for vil _fs and vih_fs specifica- tions. 50 vss_ref gnd ground for outputs. 51 xout o, se 14.318 mhz crystal output. 52 xin i 14.318 mhz crystal input. 53 vdd_ref pwr 3.3v power supply for outputs and also maintains smbus registers during power-down. 54 ref0/fsc/test_sel i/o 3.3v tolerant input for cpu f requency selection/fixed 14.318 clock output. selects test mode if pulled to v ihfs_c when ck_pwrgd is asserted high. refer to dc electrical specifications table for v ilfs_c , v imfs_c , v ihfs_c speci- fications. 55 smb_data i/o smbus compatible sdata. 56 smb_clk i smbus compatible sclock. pin definitions (continued) pin no. name type description
sl28506-2 rev 1.3 june 18, 2008 page 4 of 28 frequency select pin (fsa, fsb, and fsc) to achieve host clock frequency selection, apply th e appro- priate logic levels to fs_a, fs_b, and fs_c, inputs before ck_pwrgd assertion (as seen by the clock synthesize r). when ck_pwrgd is sampled high by the clock chip (indicating processor ck_pwrgd voltage is stable), the clock chip samples the fs_a, fs_b, and fs_c, input values . for all logic levels of fs_a, fs_b, and fs_c ck_pwrgdemploy s a one-shot functionality, in that once a valid high on ck_pwrgd has been sampled, all further ck_pwrgd fs_a, fs_b, and fs_c, transitions will be ignored, except in test mode. serial data interface to enhance the flexibility and function of the cloc k synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions, such as i ndividual clock output buffers, can be individually enabled o r disabled. the registers associated with the serial data inter face initialize to their default setting upon power-up, and therefore use of this interface is optional. clock device reg ister changes are normally made upon system initialization, if an y are required. the interface cannot be used during syste m operation for power management functions. data protocol the clock driver serial protocol accepts byte write , byte read, block write, and block read operations from the con troller. for block write/read operation, the bytes must be acces sed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any compl ete byte has been transferred. for byte write and byte read oper ations, the system controller can access individually indexed b ytes. the offset of the indexed byte is encoded in the comman d code, as described in table 2 . the block write and block read protocol is outlined in table 3 while table 4 outlines the corresponding byte write and byte read protocol. the slave receiver address is 110100 10 (d2h) . frequency select pin (fsa, fsb, and fsc) input conditions output frequency fsc fsb fsa cpu (mhz) src (mhz) sata (mhz) dot96 (mhz) usb (mhz) pci (mhz) ref (mhz) fsel_2 fsel_1 fsel_0 1 0 1 100 100 100 96 48 33.3 14.318 0 0 1 133 0 1 1 166 0 1 0 200 0 0 0 266 1 0 0 333 1 1 0 400 1 1 1 200 table 2. command code definition bit description 7 0 = block read or block write operation, 1 = byte read or byte write operation (6:0) byte offset for byte read or byte write operat ion. for block read or block write operations, thes e bits should be '0000000'
sl28506-2 rev 1.3 june 18, 2008 page 5 of 28 control registers table 3. block read and block write protocol block write protocol block read protocol bit description bit description 1 start 1 start 8:2 slave address?7 bits 8:2 slave address?7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code?8 bits 18:11 command code?8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 byte count?8 bits (skip this step if i 2 c_en bit set) 20 repeat start 28 acknowledge from slave 27:21 slave address?7 bits 36:29 data byte 1?8 bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 45:38 data byte 2?8 bits 37:30 byte count from slave?8 bits 46 acknowledge from slave 38 acknowledge .... data byte/slave acknowledges 46:39 data byte 1 fr om slave?8 bits .... data byte n?8 bits 47 acknowledge .... acknowledge from slave 55:48 data byte 2 from sla ve?8 bits .... stop 56 acknowledge .... data bytes from slave/acknowledge .... data byte n from slave?8 bits .... not acknowledge .... stop table 4. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1 start 1 start 8:2 slave address?7 bits 8:2 slave address?7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 18:11 command code?8 bits 18:11 command code?8 bits 19 acknowledge from slave 19 acknowledge from slave 27:20 data byte?8 bits 20 repeated start 28 acknowledge from slave 27:21 slave address?7 bits 29 stop 28 read 29 acknowledge from slave 37:30 data from slave?8 bits 38 not acknowledge 39 stop byte 0: control register 0 bit @pup name description
sl28506-2 rev 1.3 june 18, 2008 page 6 of 28 7 hw fs_c cpu frequency select bit, set by hw 6 hw fs_b cpu frequency select bit, set by hw 5 hw fs_a cpu frequency select bit, set by hw 4 0 iamt_en set via smbus or by combination of pwrdwn, cpu_stp, and pci_stp 0 = legacy mode, 1 = iamt enabled, sticky 1 3 0 reserved reserved 2 0 src_main_sel select source for src clock, 0 = src_main = pll1, pll3_cfb table applies 1 = src_main = pll3, pll3_cfb table does not apply 1 0 sata_sel select source of sata clock 0 = sata src_main, 1= sata pll2 0 1 pd_restore save config. in powerdown 0 = config. cleared, 1 = config. saved byte 0: control register 0 byte 1: control register 1 bit @pup name description 7 0 src0_sel select for src0 or dot96, 0 = src0, 1 = d ot96 6 0 pll1_ss_dc select for down or center ss, 0 = down spread, 1 = center spread 5 0 pll3_ss_dc select for down or center ss, 0 = down spread, 1 = center spread 4 0 pll3_cfb3 bit 4:1 only apply when src_sel=0 0000 = pll3 disable default pll3 off, src1 = src_mai n 0001 = 100 mhz 0.5% ssc stby pll3 on, src1 = src_mai n 0010 = 100 mhz 0.5% ssc only src1 sourced from pll3 0011 = 100 mhz 1.0% ssc only src1 sourced from pll3 0100 = 100 mhz 1.5% ssc only src1 sourced from pll3 0101 = 100 mhz 2.0% ssc only src1 sourced from pll3 0110 = reserved note: se clocks required to be 0111 = reserved enabled through byte 8 bit[1:0] 1000 = 1394a ( 24.576m ) on se1 and se2 1001 = 1394a ( 24.576m) on se1 and 1394b (98.304m) on se2 1010 = 1394b on se1 and se2 1011 = 27mhz_nss on se1 and se2 1100 = 25mhz on se1 and se2 1101 = 25mhz on se1 and se2 disabled (set whenpci3/cfb0 is set high to config to hw mode 3) 1110 = reserved 1111 = reserved 3 0 pll3_cfb2 2 0 pll3_cfb1 1 1 pll3_cfb0 0 1 pci_sel select pci clock source from pll1 or src_m ain 0 = pll1, 1 = src_main byte 2: control register 2 bit @pup name description 7 1 ref_oe output enable for ref 0 = output disabled, 1 = output enabled 6 1 usb_oe output enable for usb 0 = output disabled, 1 = output enabled 5 1 pcif0_oe output enable for pcif0 0 = output disabled, 1 = output enabled 4 1 pci4_oe output enable for pci4, 0 = output disable d, 1 = output enabled
sl28506-2 rev 1.3 june 18, 2008 page 7 of 28 3 1 pci3_oe output enable for pci3, 0 = output disable d, 1 = output enabled 2 1 pci2_oe output enable for pci2, 0 = output disable d, 1 = output enabled 1 1 pci1_oe output enable for pci1, 0 = output disable d, 1 = output enabled 0 1 pci0_oe output enable for pci0, 0 = output disable d, 1 = output enabled byte 2: control register 2 (continued) bit @pup name description byte 3: control register 3 bit @pup name description 7 1 src11_oe output enable for src11, 0 = output disab led, 1 = output enabled 6 1 src10_oe output enable for src10, 0 = output disab led, 1 = output enabled 5 1 src9_oe output enable for src9, 0 = output disable d, 1 = output enabled 4 1 src8/itp_oe output enable for src8 or itp, 0 = out put disabled, 1 = output enabled 3 1 src7_oe output enable for src7, 0 = output disable d, 1 = output enabled 2 1 src6_oe output enable for src6, 0 = output disable d, 1 = output enabled 1 1 src5_oe output enable for src5, 0 = output disable d, 1 = output enabled 0 1 src4_oe output enable for src4, 0 = output disable d, 1 = output enabled byte 4: control register 4 bit @pup name description 7 1 src3_oe output enable for src3, 0 = output disable d, 1 = output enabled 6 1 src2/sata_oe output enable for sata/src2, 0 = outp ut disabled, 1 = output enabled 5 1 src1_oe output enable for src, 0 = output disabled , 1 = output enabled 4 1 src0/dot96_oe output enable for src0/dot96 0 = output disabled, 1 = output enabled 3 1 cpu1_oe output enable for cpu1, 0 = output disable d, 1 = output enabled 2 1 cpu0_oe output enable for cpu0, 0 = output disable d, 1 = output enabled 1 1 pll1_ss_en enable pll1?s spread modulation, 0 = spread disabled 1 = spread enabled 0 1 pll3_ss_en enable pll3?s spread modulation 0 = spread disabled, 1 = spread enabled byte 5: control register 5 bit @pup name description 7 0 oe#_0/2_en_a enable oe#_0/2 (clk req) 0 = disabled oe#_0/2, 1 = enabled oe#_0/2, 6 0 oe#_0/2_sel_a set oe#_0/2 src0 or src2 0 = oe#_0/2 src0, 1 = oe#_0/2 src2 5 0 oe#_1/4_en_a enable oe#_1/4 (clk req) 0 = disabled oe#_1/4, 1 = enabled oe#_1/4, 4 0 oe#_1/4_sel_a set oe#_1/4 src1 or src4 0 = oe#_1/4 src1, 1 = oe#_1/4 src4 3 0 oe#_0/2_en_b enable oe#_0/2 (clk req) 0 = disabled oe#_0/2 1 = enabled oe#_0/2 2 0 oe#_0/2_sel_b set oe#_0/2 src0 or src2 0 = oe#_0/2 src0, 1 = oe#_0/2 src2 1 0 oe#_1/4_en_b enable oe#_1/4 (clk req) 0 = disabled oe#_1/4, 1 = enabled oe#_1/4,
sl28506-2 rev 1.3 june 18, 2008 page 8 of 28 0 0 oe#_1/4_sel_b set oe#_1/4 src1 or src4 0 = oe#_1/4 src1, 1 = oe#_1/4 src4 byte 5: control register 5 (continued) bit @pup name description byte 6: control register 6 bit @pup name description 7 0 oe#_6_en enable oe#_6 (clk req) src6 6 0 oe#_8_en enable oe#_8 (clk req) src8 5 0 oe#_9_en enable oe#_9 (clk req) src9 4 0 oe#_10_en enable oe#_10 (clk req) src10 3 0 reserved reserved 2 0 reserved reserved 1 0 lcd_100_stp_ctrl allows control of lcd_100 with as sertion of pci_stop# 0 = free runninglcd_100, 1 = stopped with pci_stop# 0 0 src_stp_ctrl allows control of src with assertion of pci_stop# 0 = free running src 1 = stopped with pci_stop# byte 7: vendor id bit @pup name description 7 0 rev code bit 3 revision code bit 3 6 0 rev code bit 2 revision code bit 2 5 0 rev code bit 1 revision code bit 1 4 1 rev code bit 0 revision code bit 0 3 1 vendor id bit 3 vendor id bit 3 2 0 vendor id bit 2 vendor id bit 2 1 0 vendor id bit 1 vendor id bit 1 0 0 vendor id bit 0 vendor id bit 0 byte 8: control register 8 bit @pup name description 7 0 device_id3 0000 = ck505 yellow cover device, 56-pi n tssop 0001 = ck505 yellow cover device, 64-pin tssop 0010 = ck505 yellow cover device, 48-pin qfn (reser ved) 0011 = ck505 yellow cover device, 56-pin qfn (reser ved) 0100 = ck505 yellow cover device, 64-pin qfn (reser ved) 0101 = ck505 yellow cover device, 72-pin qfn (reser ved) 0110 = ck505 yellow cover device, 48-pin ssop (rese rved) 0111 = ck505 yellow cover device, 56-pin ssop (rese rved) 1000 = reserved 1001 = reserved 1010 = reserved 1011 = reserved 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved 7 0 device_id2 5 0 device_id1 4 0 device_id0 3 0 reserved reserved 2 0 reserved reserved 1 0 se1_oe se1 output enable 0 = output disabled, 1 = output enabled 0 0 se2_oe se2 output enable 0 = output disabled, 1 = output enabled
sl28506-2 rev 1.3 june 18, 2008 page 9 of 28 byte 9 control register 9 bit @pup name description 7 0 pcif0_stp_ctrl allows control of pcif0 with assert ion of pci_stop# 0 = free running pcif, 1 = stopped with pci_stop# 6 hw_pin tme_strap trusted mode enable strap status, 0 = normal, 1 = no overclocking 5 1 ref_bit1 ref drive strength control, see byte 18 for more setting 0 = low, 1 = high 4 0 test_mode_sel mode select either ref/n or tri-stat e 0 = all output tri-state, 1 = all output ref/n 3 0 test_mode_entry allow entry into test mode 0=normal operation, 1=enter test mode 2 1 io_vout2 io_vout[2,1,0] 000 = 0.3v 001 = 0.4v 010 = 0.5v 011 = 0.6v 100 = 0.7v 101 = 0.8v, default 110 = 0.9v 111 = 1.0v 1 0 io_vout1 0 1 io_vout0 byte 10 control register 10 bit @pup name description 7 hw src5_en_strap read only bit for src5_en_strap 0 = cpu/pci_stop enabled, 1 = src5 pair enabled 6 1 pll3_en pll3 enabled 0 = pll3 disabled, 1 = pll3 enabled 5 1 pll2_en pll2 enabled 0 = pll2 disabled, 1 = pll2 enabled 4 1 src_div_en src divider enabled 0 = src divider disabled, 1 = src divider enabled 3 1 pci_div_en pci divider enabled 0 = pci divider disabled, 1 = pci divider enabled 2 1 cpu_div_en cpu divider enabled 0 = cpu divider disabled, 1 = cpu divider enabled 1 1 cpu1_stp_crtl allow control of cpu1 with assertion of cpu_stop# 0 = free running, 1 = stopped with cpu_stop# 0 1 cpu0_stp_crtl allow control of cpu0 with assertion of cpu_stop# 0 = free running, 1 = stopped with cpu_stop# byte 11 control register 11 bit @pup name description 7 hw pci3_cfg1 6 hw pci3_cfg0 output ssc output ssc output ssc 0 0 0 -def cpu / src / pci33 down usb na -- -- 0 1 1 cpu down usb na src/pci33 down 1 0 2 cpu center usb na src/pci33 down 1 1 3 cpu center usb/25m na src/pci33 down pll2 pll3 pci3/ cgf1 pci3/ cgf0 mode pll1
sl28506-2 rev 1.3 june 18, 2008 page 10 of 28 5 0 25mhz_en_se1 25mhz output enabled applies to power down / m1 (only applies when pci3/cgfg0 strap is set high to enter hw mode 3) 0 = 25mhz disabled in powerdown / m1 1 = 25mhz enabled in powerdown / m1; sticky 1 4 1 reserved reserved 3 0 cpu2_amt_en 2 1 cpu1_amt_en 1 hw pci-e_gen2 pci-e_gen2 compliant 0 = non gen2, 1= gen2 compliant 0 1 cpu2_stp_crtl allow control of cpu2 with assertion of cpu_stop# 0 = free running, 1 = stopped with cpu_stop# byte 11 control register 11 pcif0/itp_en amt_en cpu2_amt_en cpu1_amt_en description x 1 0 0 reserved x 1 0 1 cpu1 = m1 clock 1 1 1 0 cpu2 - m1 clock 1 1 1 1 cpu1 and cpu2 = m1 clock byte 12 byte count bit @pup name description 7 0 reserved reserved 6 0 reserved reserved 5 0 bc5 byte count 4 0 bc4 byte count 3 1 bc3 byte count 2 1 bc2 byte count 1 0 bc1 byte count 0 1 bc0 byte count byte 13 control register 13 bit @pup name description 7 1 usb_bit1 usb drive strength control, see byte 18 for more setting 0 = low, 1= high 6 1 pci/pcif_bit1 pci drive strength control, see byte 18 for more setting 0 = low, 1 = high 5 0 reserved reserved 4 0 sata_ss_en enable sata spread modulation, 0 = spread disabled 1 = spread enabled 3 1 en_cfg0_set by defalult cfg0 pin strap sets the sm bus initial values to select the hw mode. when this bit is written0, subsequent smbus a ccesses is the lathes open state, can overwrite the cfg0 pin setting into the smbus bits and set the mode before the m0 state: specifically b0b2, b1 b[6,4,3], b9b1, b11b5 2 1 se1/se2_bit1 se1 and se2 drive strength control, see byte 18 for more setting 0 = low, 1 = high 1 1 reserved reserved
sl28506-2 rev 1.3 june 18, 2008 page 11 of 28 0 1 sw_pci sw pci_stp# function 0 = sw pci_stp assert, 1 = sw pci_stp deassert when this bit is set to 0, all stoppable pci, pcif and src outputs will be stopped in a synchronous manner with no short pu lses. when this bit is set to 1, all stopped pci, pcif an d src outputs will resume in a synchronous manner with no short pulses . byte 13 control register 13 byte 14 control register 14 bit @pup name description 7 0 cpu_daf_n7 if prog_cpu_en is set, the values progr ammed in cpu_daf_n[8:0] and cpu_daf_m[6:0] will be used to determine the cpu ou tput frequency. the setting of the fs_override bit determines the frequ ency ratio for cpu and other output clocks. when it is cleared, the same f requency ratio stated in the latched fs[c:a] register will be used. when it is set, the frequency ratio stated in the fsel[2:0] register will be used 6 0 cpu_daf_n6 5 0 cpu_daf_n5 4 0 cpu_daf_n4 3 0 cpu_daf_n3 2 0 cpu_daf_n2 1 0 cpu_daf_n1 0 0 cpu_daf_n0 byte 15 control register 15 bit @pup name description 7 0 cpu_daf_n8 see byte 14 for description 6 0 cpu_daf_m6 if prog_cpu_en is set, the values progr ammed are in cpu_fsel_n[8:0] and cpu_fsel_m[6:0] will be used to determine the c pu output frequency. the setting of the fs_override bit deter mines the frequency ratio for cpu and other output clocks. when it is c leared, the same frequency ratio stated in the latched fs[c:a] regis ter will be used. when it is set, the frequency ratio stated in the fsel[2:0] register will be used 5 0 cpu_daf_m5 4 0 cpu_daf_m4 3 0 cpu_daf_m3 2 0 cpu_daf_m2 1 0 cpu_daf_m1 0 0 cpu_daf_m0 byte 16 control register 16 bit @pup name description 7 0 pci-e_n7 if prog_src_en is set, the values program med in src_daf_n[7:0] will be used to determine the src output frequency. 6 0 pci-e_n6 5 0 pci-e_n5 4 0 pci-e_n4 3 0 pci-e_n3 2 0 pci-e_n2 1 0 pci-e_n1 0 0 pci-e_n0 byte 17 control register 17 bit @pup name description 7 0 smsw_en enable smooth switching, 0 = disabled, 1= enabled 6 0 smsw_sel smooth switch select, 0 = cpu_pll, 1 = sr c_pll 5 0 reserved reserved
sl28506-2 rev 1.3 june 18, 2008 page 12 of 28 byte 18 control register 18 the sl28506-2 requires a parallel resonance crystal . substi- tuting a series resonance crystal causes the sl2850 6-2 to operate at the wrong frequency and violate the ppm specifi- cation. for most applications there is a 300-ppm fr equency shift between series and parallel crystals due to i ncorrect loading. crystal loading crystal loading plays a critical role in achieving low ppm perfor- mance. to realize low ppm performance, the total ca pacitance the crystal sees must be considered to calculate th e appro- priate capacitive loading (cl). figure 1 shows a typical crystal configuration using the tw o trim capacitors. an important clarification for the following discussion is that the trim capacitors are in serie s with the crystal not parallel. the common misconception that load capacitors are in parallel with the crystal and sho uld be approximately equal to the load capacitance of the crystal is not true. calculating load capacitors in addition to the standard external trim capacitor s, trace capacitance and pin capacitance must also be consid ered to correctly calculate crystal loading. as mentioned p reviously, the capacitance on each side of the crystal is in s eries with the crystal. this means the total capacitance on each s ide of the crystal must be twice the specified crystal load ca pacitance (cl). while the capacitance on each side of the cry stal is in series with the crystal, trim capacitors (ce1,ce2) should be calculated to provide equal capacitive loading on b oth sides. 4 0 prog_pci-e_en programmable pci-e frequency enable 0 = disabled, 1= enabled 3 0 prog_cpu_en programmable cpu frequency enable 0 = disabled, 1= enabled 2 0 reserved reserved 1 0 reserved reserved 0 0 reserved reserved byte 17 control register 17 bit @pup name description 7 0 pci_bit2 drive strength control - dsc[2:0] 6 1 pci_bit0 5 0 usb_bit2 4 0 usb_bit0 3 0 se1/se2_bit2 2 0 se1/se2_bit0 1 0 ref_bit2 0 0 ref_bit0 table 5. crystal recommendations frequency (fund) cut loading load cap drive (max.) shunt cap (max.) motional (max.) tolerance (max.) stability (max.) aging (max.) 14.31818 mhz at parallel 20 pf 0.1 mw 5 pf 0.016 pf 35 ppm 30 ppm 5 ppm bit_2 (byte18) bit_1 (vario us b ytes) bit_0 (byte 18) buff er strength 1 1 1 strongest 1 1 0 1 0 1 1 0 0 default pci 0 1 1 default ref/usb 0 1 0 0 0 1 0 0 0 weakest figure 1. crystal capacitive clarification
sl28506-2 rev 1.3 june 18, 2008 page 13 of 28 use the following formulas to calculate the trim ca pacitor values for ce1 and ce2. cl ................................................. .. crystal load capacitance cle .........................................actual loading seen by crystal using standard value trim capacitors ce ................................................. ....external trim capacitors cs ............................................. stra y capacitance (terraced) ci ................................................ .......... internal capacitance (lead frame, bond wires etc.) dial-a-frequency (cpu & pciex) this feature allows users to over-clock their syste ms by slowly stepping up the cpu or src frequency. when the prog ram- mable output frequency feature is enabled, the cpu and src frequencies are determined by the following equatio n: fcpu = g * n/m or fcpu=g2 * n, where g2 = g/m. ?n? and ?m? are the values programmed in programmab le frequency select n-value register and m-value regis ter, respectively. ?g? stands for the pll gear constant, which is determined by the programmed value of fs[e:a]. see frequency table for the gear constant for each frequency selection. the pci express only allows user control of the n register, the m value is fixed and documented in th e frequency select table . in this mode, the user writes the desired n and m v alue into the daf i2c registers. the user cannot change only the m value and must change both the m and the n values a t the same time, if they require a change to the m value. the user may change only the required n value. associated register bits cpu_daf enable ? this bit enables cpu daf mode. by default, it is not set. when set, the operating fre quency is determined by the values entered into the cpu_daf_n register. note that the cpu_daf_n and m register mu st contain valid values before cpu_daf is set. default = 0, (no daf). cpu_daf_n ? there are nine bits (for 512 values) to linearly change the cpu frequency (limited by vco range). de fault = 0, (0000). the allowable values for n are detailed in the frequency select table . cpu daf m ? there are 7 bits (for 128 values) to li nearly change the cpu frequency (limited by vco range). de fault = 0, the allowable values for m are detailed in the frequency select table . src_daf enable ? this bit enables src daf mode. by default, it is not set. when set, the operating fre quency is determined by the values entered into the src_daf_n register. note that the src_daf_n register must con tain valid values before src_daf is set. default = 0, (no daf) . src_daf_n ? there are nine bits (for 512 values) to linearly change the cpu frequency (limited by vco range). de fault = 0, (0000). the allowable values for n are detailed in the frequency select table . smooth switching the device contains 1 smooth switch circuit that is shared by the cpu pll and src pll. the smooth switch circuit ensures that when the output frequency changes by overclock ing, the transition from the old frequency to the new freque ncy is a slow, smooth transition containing no glitches. the rate of change of output frequency when using the smooth sw itch circuit is less than 1 mhz/0.667 s. the frequency overshoot and undershoot is less than 2%. the smooth switch circuit can be assigned as auto o r manual. in auto mode, clock generator will assign smooth sw itch automatically when the pll does overclocking. for m anual mode, the smooth switch circuit can be assigned to either pll via smbus. by default the smooth switch circuit is set to auto mode. either pll can still be over-clocked when it does not have control of the smooth switch circuit but it is not guaranteed to transition to the new frequency witho ut large frequency glitches. it is not recommended to enable over-clocking and c hange the n values of both plls in the same smbus block write and use smooth switch mechanism on spread spectrum on/off. pd# clarification the ck_pwrgd/pd# pin is a dual-function pin. during initial power-up, the pin functions as ck_pwrgd. once ck_pwrgd has been sampled high by the clock chip, t he pin assumes pd# functionality. the pd# pin is an asynchronous active low input used to shut off all clocks cleanly prior to shutting off power to the device. this signal is synchronized internal to the device prior to poweri ng down the clock synthesizer. pd# is also an asynchronous inpu t for powering up the system. when pd# is asserted low, a ll clocks need to be driven to a low value and held pr ior to turning off the vcos and the crystal oscillator. xtal ce2 ce1 cs1 cs2 x 1 x 2 ci1 ci2 c lock c hip trace 2.8 pf trim 33 pf pin 3 to 6p figure 2. crystal loading example load capacitance (each side) total capacitance (as seen by the crystal) ce = 2 * cl ? (cs + ci) ce1 + cs1 + ci1 1 + ce2 + cs2 + ci2 1 ( ) 1 = cle
sl28506-2 rev 1.3 june 18, 2008 page 14 of 28 pd assertion when ps is sampled high by two consecutive rising e dges of cpuc, all single-ended outputs will be held low on their next high-to-low transition and differential clocks must held low. in the event that pd mode is desired as the in itial power-on state, pd must be asserted high in less th an 10 s after asserting ck_pwrgd. pd# deassertion the power-up latency is less than 1.8 ms. this is t he time from the deassertion of the pd# pin or the ramping of th e power supply until the time that stable clocks are output from the clock chip. all differential outputs stopped in a t hree-state condition resulting from power down will be driven high in less than 300 s of pd# deassertion to a voltage greater than 200 mv. after the clock chip?s internal pll is power ed up and locked, all outputs will be enabled within a few cl ock cycles of each other. below is an example showing the relatio nship of clocks coming up. cpu_stp# assertion the cpu_stp# signal is an active low input used to synchronously stop and start the cpu output clocks while the rest of the clock generator continues to function. when the cpu_stp# pin is asserted, all cpu outputs that are set with the smbus configuration to be stoppable via asserti on of cpu_stp# are stopped within two to six cpu clock pe riods after being sampled by two rising edges of the inte rnal cpuc clock. the final states of the stopped cpu signals are cput = high and cpuc = low. pd# usb, 48mhz dot96t dot96c srct 100mhz srcc 100mhz cput, 133mhz pci, 33 mhz ref cpuc, 133mhz figure 3. pd assertion timing waveform dot96c pd# cpuc, 133mhz cput, 133mhz srcc 100mhz usb, 48mhz dot96t srct 100mhz tstable <1.8ms pci, 33mhz ref tdrive_pw rdn# <300 s, >200mv pd deassertion timing waveform
sl28506-2 rev 1.3 june 18, 2008 page 15 of 28 cpu_stp# deassertion the deassertion of the cpu_stp# signal will cause a ll cpu outputs that were stopped to resume normal operatio n in a synchronous manner, synchronous manner meaning that no short or stretched clock pulses will be produce whe n the clock resumes. the maximum latency from the deassertion t o active outputs is no more than two cpu clock cycles. c p u _s t p # c p u t c p u c figure 4. cpu_stp# assertion waveform cpu _stp# cp ut cp uc cp ut internal tdrive_c pu_stp#,10 ns>2 00 mv cp uc internal cpu_stp# deassertion waveform cpuc(stoppable) cput(stoppable) cpuc(free running cput(free running pd# 1.8ms cpu_stop# dot96c dot96t cpu_stp# = driven, cpu_pd = driven, dot_pd = driven
sl28506-2 rev 1.3 june 18, 2008 page 16 of 28 pci_stp# assertion the pci_stp# signal is an active low input used to synchro- nously stop and start the pci outputs while the res t of the clock generator continues to function. the set-up time fo r capturing pci_stp# going low is 10 ns (t su ). (see figure 5 .) the pcif clocks will not be affected by this pin if their co rresponding control bit in the smbus register is set to allow t hem to be free running. pci_stp# deassertion the deassertion of the pci_stp# signal causes all p ci and stoppable pcif clocks to resume running in a synchr onous manner within two pci clock periods after pci_stp# transi- tions to a high level. dot96c dot96t cpuc(free running) cput(free running) cpuc(stoppable) cput(stoppable) pd# 1.8ms cpu_stop# cpu_stp# = tri-state, cpu_pd = tri-state, dot_pd = tri-state t su pc i_s t p# pc i_ f p c i s r c 1 0 0m h z figure 5. pci_stp# assertion waveform pci_stp# pci_f pci src 100mhz tsu tdrive_src figure 6. pci_stp# deassertion waveform
sl28506-2 rev 1.3 june 18, 2008 page 17 of 28 . pd_restore if a ?0? is set for byte 0 bit 0 then, upon asserti on of pwrdwn# low, the cy505 will initiate a full reset. the resu lts of this will be that the clock chip will emulate a cold power on start and go to the ?latches open? state. if the pd_restore b it is set to a ?1? then the configuration is stored upon pwrd wn# asserted low. note that if the iamt bit, byte 0 bit 3, is set to a ?1? then the pd_restore bit must be ignored. in o ther words, in intel iamt mode, pwrdwn# reset is not all owed. figure 7. ck_pwrgd timing diagram table 6. output driver status during pci-stop# and c pu-stop# pci_stop# asserted cpu_stop# asserted smbus oe disabl ed single-ended clocks stoppable driven low running driven low non stoppable running running differential clocks stoppable clock drive high clock# driven low clock drive high clock# driven low driven low or 20k pulldown non stoppable running running table 7. output driver status all single-ended clocks all differential clocks exce pt cpu1 cpu1 w/o strap w/strap clock clock# clock clock# latches open state low hi-z low or 20k pulldown low low or 20k pulldown low powerdown low hi-z low or 20k pulldown low low or 20k pu lldown low m1 low hi-z low or 20k pulldown low running running
sl28506-2 rev 1.3 june 18, 2008 page 18 of 28 figure 8. clock generator power-up/run state diagra m
sl28506-2 rev 1.3 june 18, 2008 page 19 of 28 absolute maximum conditions parameter description condition min. max. unit v dd core supply voltage ?0.5 4.6 v v dd_a analog supply voltage ?0.5 4.6 v v dd_io io supply voltage 1.5 v v in input voltage relative to v ss ?0.5 4.6 v dc t s temperature, storage non-functional ?65 150 c t a temperature, operating ambient functional 0 70 c t j temperature, junction functional ? 150 c ? jc dissipation, junction to case mil-std-883e method 10 12.1 ? 20 c/w ? ja dissipation, junction to ambient jedec (jesd 51) ? 60 c/w esd hbm esd protection (human body model) mil-std-883, metho d 3015 2000 ? v ul-94 flammability rating at 1/8 in. v?0 msl moisture sensitivity level 1 multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequenc ing is not required. dc electrical specifications parameter description condition min. max. unit vdd core 3.3v operating voltage 3.3 5% 3.135 3.465 v v ih 3.3v input high voltage (se) 2.0 v dd + 0.3 v v il 3.3v input low voltage (se) v ss ?0.3 0.8 v v ihi2c input high voltage sdata, sclk 2.2 ? v v ili2c input low voltage sdata, sclk ? 1.0 v v ih_fs fs_[a,b] input high voltage 0.7 1.5 v v il_fs fs_[a,b] input low voltage v ss ?0.3 0.35 v v ihfs_c_test fs_c input high voltage 2 v dd + 0.3 v v imfs_c_normal fs_c input middle voltage 0.7 1.5 v v ilfs_c_normal fs_c input low voltage v ss ?0.3 0.35 v pci3/cfg0 _high pci3/cfg0 input high voltage typ. 2.75v 2.40 vdd v pci3/cfg0 _mid pci3/cfg0 input mid voltage typ. 1.65v 1.30 2.00 v pci3/cfg0 _low pci3/cfg0 input low voltage typ. 0.550v 0 0.900 v i ih input high leakage current except internal pull-down resistors, 0< v in sl28506-2 rev 1.3 june 18, 2008 page 20 of 28 ac electrical specifications parameter description condition min. max. unit crystal t dc xin duty cycle the device will operate reliably with input duty cycles up to 30/70 but the ref clock duty cycle will not be within specification 47.5 52.5 % t period xin period when xin is driven from an external clock source 69.841 71.0 ns t r /t f xin rise and fall times measured between 0.3v dd and 0.7v dd ? 10.0 ns t ccj xin cycle to cycle jitter as an average over 1- s duration ? 500 ps l acc long-term accuracy ? 300 ppm cpu at 0.7v t dc cput and cpuc duty cycle measured at 0v differential @ 0.1s 45 55 % t period 100 mhz cput and cpuc period measured at 0v differen tial @ 0.1s 9.99900 10.0100 ns t period 133 mhz cput and cpuc period measured at 0v differen tial @ 0.1s 7.49925 7.50075 ns t period 166 mhz cput and cpuc period measured at 0v differen tial @ 0.1s 5.99940 6.00060 ns t period 200 mhz cput and cpuc period measured at 0v differen tial @ 0.1s 4.99950 5.00050 ns t period 266 mhz cput and cpuc period measured at 0v differen tial @ 0.1s 3.74963 3.75038 ns t period 333 mhz cput and cpuc period measured at 0v differen tial @ 0.1s 2.99970 3.00030 ns t period 400 mhz cput and cpuc period measured at 0v differen tial @ 0.1s 2.49975 2.50025 ns t periodss 100 mhz cput and cpuc period, ssc measured at 0v dif ferential @ 0.1s 10.02406 10.02607 ns t periodss 133 mhz cput and cpuc period, ssc measured at 0v dif ferential @ 0.1s 7.51804 7.51955 ns t periodss 166 mhz cput and cpuc period, ssc measured at 0v dif ferential @ 0.1s 6.01444 6.01564 ns t periodss 200 mhz cput and cpuc period, ssc measured at 0v dif ferential @ 0.1s 5.01203 5.01303 ns t periodss 266 mhz cput and cpuc period, ssc measured at 0v dif ferential @ 0.1s 3.75902 3.75978 ns t periodss 333 mhz cput and cpuc period, ssc measured at 0v dif ferential @ 0.1s 3.00722 3.00782 ns t periodss 400 mhz cput and cpuc period, ssc measured at 0v dif ferential @ 0.1s 2.50601 2.50652 ns t periodabs 100 mhz cput and cpuc absolute period measured at 0v differential @ 1 clock 9.91400 10.0860 ns t periodabs 133 mhz cput and cpuc absolute period measured at 0v differential @ 1 clock 7.41425 7.58575 ns t periodabs 166 mhz cput and cpuc absolute period measured at 0v differential @ 1 clock 5.91440 6.08560 ns t periodabs 200 mhz cput and cpuc absolute period measured at 0v differential @ 1 clock 4.91450 5.08550 ns t periodabs 266 mhz cput and cpuc absolute period measured at 0v differential @ 1 clock 3.66463 3.83538 ns t periodabs 333 mhz cput and cpuc absolute period measured at 0v differential @ 1 clock 2.91470 3.08530 ns t periodabs 400 mhz cput and cpuc absolute period measured at 0v differential @ 1 clock 2.41475 2.58525 ns t periodssabs 100 mhz cput and cpuc absolute period, ssc measured at 0v differential @ 1 clock 9.91406 10.1362 ns t periodssabs 133 mhz cput and cpuc absolute period, ssc measured at 0v differential @ 1 clock 7.41430 7.62340 ns t periodssabs 166 mhz cput and cpuc absolute period, ssc measured at 0v differential @ 1 clock 5.91444 6.11572 ns t periodssabs 200 mhz cput and cpuc absolute period, ssc measured at 0v differential @ 1 clock 4.91453 5.11060 ns t periodssabs 266 mhz cput and cpuc absolute period, ssc measured at 0v differential @ 1 clock 3.66465 3.85420 ns t periodssabs 333 mhz cput and cpuc absolute period, ssc measured at 0v differential @ 1 clock 2.91472 3.10036 ns t periodssabs 400 mhz cput and cpuc absolute period, ssc measured at 0v differential @ 1 clock 2.41477 2.59780 ns t ccj cput/c cycle to cycle jitter measured at 0v differen tial ? 85 ps t ccj2 cpu2_itp cycle to cycle jitter measured at 0v differ ential ? 125 ps l acc long-term accuracy measured at 0v differential ? 100 pp m t skew2 cpu2_itp to cpu0 clock skew measured at 0v different ial ? 100 ps t skew2 cpu2_itp to cpu0 clock skew measured at 0v different ial ? 150 ps
sl28506-2 rev 1.3 june 18, 2008 page 21 of 28 t r /t f cput and cpuc rise and fall time measured differenti ally from 150 mv 2.5 8 v/ns t rfm rise/fall matching measured single-endedly from 75 mv ? 20 % v high voltage high 1.15 v v low voltage low ?0.3 ? v v ox crossing point voltage at 0.7v swing 300 550 mv src t dc srct and srcc duty cycle measured at 0v differential 45 55 % t period 100 mhz srct and srcc period measured at 0v differen tial @ 0.1s 9.99900 10.0010 ns t periodss 100 mhz srct and srcc period, ssc measured at 0v di fferential @ 0.1s 10.02406 10.02607 ns t periodabs 100 mhz srct and srcc absolute period measured at 0v differential @ 1 clock 9.87400 10.1260 ns t periodssabs 100 mhz srct and srcc absolute period, ssc measured at 0v differential @ 1 clock 9.87406 10.1762 ns t skew(window) any srct/c to srct/c clock skew from the earliest bank to the latest bank measured at 0v differential ? 3.0 ns t ccj srct/c cycle to cycle jitter measured at 0v differen tial ? 125 ps l acc srct/c long term accuracy measured at 0v differentia l ? 100 ppm t r /t f srct and srcc rise and fall time measured differenti ally from 150 mv 2.5 8 v/ns t rfm rise/fall matching measured single-endedly from 75 mv ? 20 % v high voltage high 1.15 v v low voltage low ?0.3 ? v v ox crossing point voltage at 0.7v swing 300 550 mv dot t dc dot96t and dot96c duty cycle measured at 0v differen tial 45 55 % t period dot96t and dot96c period measured at 0v differential @ 0.1s 10.4156 10.4177 ns t periodabs dot96t and dot96c absolute period measured at 0v dif ferential @ 0.1s 10.1656 10.6677 ns t ccj dot96t/c cycle to cycle jitter measured at 0v differ ential @ 1 clock ? 250 ps l acc dot96t/c long term accuracy measured at 0v different ial @ 1 clock ? 300 ppm t r /t f dot96t and dot96c rise and fall time measured differ entially from 150 mv 2.5 8 v/ns t rfm rise/fall matching measured single-endedly from 75 mv ? 20 % v high voltage high 1.15 v v low voltage low ?0.3 ? v v ox crossing point voltage at 0.7v swing 300 550 mv lcd_100_ssc t dc ssct and sscc duty cycle measured at 0v differential 45 55 % t period 100 mhz ssct and sscc period measured at 0v differen tial @ 0.1s 9.99900 10.0010 ns t periodss 100 mhz ssct and sscc period, ssc measured at 0v di fferential @ 0.1s 10.02406 10.02607 ns t periodabs 100 mhz ssct and sscc absolute period measured at 0v differential @ 1 clock 9.87400 10.1260 ns t periodssabs 100 mhz srct and srcc absolute period, ssc measured at 0v differential @ 1 clock 9.87406 10.1762 ns t ccj ssct/c cycle to cycle jitter measured at 0v differential ? 250 ps l acc ssct/c long term accuracy measured at 0v differential ? 300 ppm t r /t f ssct and sscc rise and fall time measured differentially from 150 mv 2.5 8 v/ns t rfm rise/fall matching measured single-endedly from 75 mv ? 20 % v high voltage high 1.15 v v low voltage low ?0.3 ? v ac electrical specifications (continued) parameter description condition min. max. unit
sl28506-2 rev 1.3 june 18, 2008 page 22 of 28 v ox crossing point voltage at 0.7v swing 300 550 mv pci/pcif t dc pci duty cycle measurement at 1.5v 45 55 % t period spread disabled pcif/pci period measurement at 1.5v 29.99100 30.00900 ns t periodss spread enabled pcif/pci period, ssc measurement at 1.5v 30.08421 30.23459 ns t periodabs spread disabled pcif/pci period measurement at 1.5v 29.49700 30.50300 ns t periodssabs spread enabled pcif/pci period, ssc measurement at 1.5v 29.56617 30.58421 ns t high pcif and pci high time measurement at 2.4v 12.0 ? ns t low pcif and pci low time measurement at 0.4v 12.0 ? ns t r /t f pcif/pci rising and falling edge rate measured between 0.8v and 2.0v 1.0 4.0 v/ns t skew any pci clock to any pci clock skew measurement at 1.5v ? 1000 ps t ccj pcif and pci cycle to cycle jitter measurement at 1.5v ? 500 ps l acc pcif/pci long term accuracy measurement at 1.5v ? 100 ppm 48_m t dc duty cycle measurement at 1.5v 45 55 % t period period measurement at 1.5v 20.83125 20.83542 ns t periodabs absolute period measurement at 1.5v 20.48125 21.18542 ns t high 48_m high time measurement at 2.4v 8.216563 11.15198 ns t low 48_m low time measurement at 0.4v 7.816563 10.95198 ns t r /t f rising and falling edge rate measured between 0.8v and 2.0v 1.0 2.0 v/ns t ccj cycle to cycle jitter measurement at 1.5v ? 350 ps l acc 48m long term accuracy measurement at 1.5v ? 100 ppm 25_m t dc duty cycle measurement at 1.5v 45 55 % t period period measurement at 1.5v 39.996 40.004 ns t r /t f rising and falling edge rate measured between 0.8v and 2.0v 1.0 4.0 v/ns t ccj cycle to cycle jitter measurement at 1.5v ? 500 ps l acc 25m long term accuracy measurement at 1.5v ? 50 ppm 27_m t dc duty cycle measurement at 1.5v 45 55 % t period period measurement at 1.5v 37.03594 37.03813 ns t r /t f rising and falling edge rate measured between 0.8v and 2.0v 1.0 4.0 v/ns t ccj cycle to cycle jitter measurement at 1.5v ? 500 ps l acc 27m long term accuracy measurement at 1.5v ? 30 ppm t ltj @ 1 s 27m long term jitter @ 10 s measurement at 1.5v @ 1 s ? 500 ps 1394a - 24.576m t dc duty cycle measurement at 1.5v 45 55 % t period period measurement at 1.5v 40.686 40.694 ns t r /t f rising and falling edge rate measured between 0.8v and 2.0v 1.0 4.0 v/ns t ccj cycle to cycle jitter measurement at 1.5v ? 200 ps l acc 24m long term accuracy measurement at 1.5v ?30 30 ppm 1394b - 98.304m t dc duty cycle measurement at 1.5v 45 55 % t period period measurement at 1.5v 10.1735 10.1715 ns ac electrical specifications (continued) parameter description condition min. max. unit
sl28506-2 rev 1.3 june 18, 2008 page 23 of 28 test and measurement set-up for pci single-ended signals and reference the following diagram shows the test load configura tions for the single-ended pci, usb, and ref output signals. t r /t f rising and falling edge rate measured between 0.8v and 2.0v 1.0 4.0 v/ns t ccj cycle to cycle jitter measurement at 1.5v ? 200 ps l acc 98m long term accuracy measurement at 1.5v ?30 30 ppm ref t dc ref duty cycle measurement at 1.5v 45 55 % t period ref period measurement at 1.5v 69.82033 69.86224 ns t periodabs ref absolute period measurement at 1.5v 68.83429 70.84826 ns t high ref high time measurement at 2v 29.97543 38.46654 ns t low ref low time measurement at 0.8v 29.57543 38.26654 ns t r /t f ref rising and falling edge rate measured between 0.8v and 2.0v 1.0 4.0 v/ns t skew ref clock to ref clock measurement at 1.5v ? 500 ps t ccj ref cycle to cycle jitter measurement at 1.5v ? 1000 ps l acc long term accuracy measurement at 1.5v ? 100 ppm enable/disable and set-up t stable clock stabilization from power-up ? 1.8 ms t ss stopclock set-up time 10.0 ? ns ac electrical specifications (continued) parameter description condition min. max. unit 22 measurement point 4 pf 50 22 measurement point 4 pf 50 pci/usb l 1 l 2 l 1 l 2 l1 = 0.5", l2 = 8" figure 9. single-ended pci and usb double load conf iguration 50 15 measurement point 4 pf 50 15 measurement point 4 pf 50 ref l 2 l 2 l1 l1 l 2 15 measurement point 4 pf l1 figure 10. single-ended ref triple load configurati on
rev 1.3, june 18, 2008 page 24 of 28 sl28506-2 figure 11. single-ended output signals (for ac para meters measurement)
sl28506-2 rev 1.3 june 18, 2008 page 25 of 28 for cpu, src, and dot96 signals and reference the following diagram shows the test load configura tion for the differential cpu and src outputs. 33 measurement point 2 pf 50 l1 l 2 33 measurement point 2 pf 50 l1 l 2 l1 = 0.5", l2 = 7" out+ out- figure 12. 0.7v differential load configuration figure 13. differential measurement for differentia l output signals (for ac parameters measuremement figure 14. single-ended measurement for differentia l output signals (for ac parameters measurement)
sl28506-2 rev 1.3 june 18, 2008 page 26 of 28 ordering information part number package type product flow lead-free sl28506bzc-2 56-pin tssop commercial, 0 to 70 c sl28506bzc-2t 56-pin tssop?tape and reel commercial, 0 to 70 c sl28506boc-2 56-pin ssop commercial, 0 to 70 c SL28506BOC-2T 56-pin ssop?tape and reel commercial, 0 to 70 c packaging designator for tape and reel temperature designator package designator z : tssop; l : qfn; o: ssop die revision designator a = 1 st revision; b = 2 nd revision...... generic part number designated family number company initials derivatives of a generic part sl 28 506 b z c yyy t ( die rev. not correlated to datasheet version) this device is pb free and halogen free and rohs co mpliant. devices supporting extended temperature is availabl e upon request.
sl28506-2 rev 1.3 june 18, 2008 page 27 of 28 package diagram 56-lead thin shrunk small outline package, type ii (6 mm x 12 mm) z56 56-lead shrunk small outline package o56 while sli has reviewed all information herein for a ccuracy and reliability, spectra linear inc. assume s no responsibility for the use of any cir- cuitry or for the infringement of any patents or ot her rights of third parties which would result from each use. this product is intended for use in normal commercial applications and is not warran ted nor is it intended for use in life support, cri tical medical instruments, or any other application requiring extended temperature range, h igh reliability, or any other extraordinary environ mental requirements unless pursuant to additional processing by spectra linear inc., and e xpressed written agreement by spectra linear inc. s pectra linear inc. reserves the right to change any circuitry or specification without no tice.
sl28506-2 rev 1.3 june 18, 2008 page 28 of 28 document history page document title: sl28506-2 clock generator for intel ? ?? ? eaglelake chipset rev. issue date orig. of change description of change 1.0 7/12/07 jma new data sheet 1.1 7/18/07 jma merge tssop and ssop into one datashee t 1.2 7/19/07 jma changed part number ordering informati on 1.3 6/18/08 jma 1. removed ?priliminary confidential? wording 2. change ordering information 3. change operating temperature from 0c - 85c to 0c to 70c 4. add pb and rohs compliant note

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